diff --git a/sources/zweic/Generator.scala b/sources/zweic/Generator.scala index 2640bed..e0911cb 100644 --- a/sources/zweic/Generator.scala +++ b/sources/zweic/Generator.scala @@ -161,24 +161,22 @@ case Binop(op, left, right) => genTmp { tmpLeft => genLoad(left, tmpLeft); - genTmp { tmpRight => - genLoad(right, tmpRight); + genLoad(right, targetReg); op match { case Operators.ADD => - code.emit(ADD, targetReg, tmpLeft, tmpRight, "+"); + code.emit(ADD, targetReg, tmpLeft, targetReg, "+"); case Operators.SUB => - code.emit(SUB, targetReg, tmpLeft, tmpRight, "-"); + code.emit(SUB, targetReg, tmpLeft, targetReg, "-"); case Operators.MUL => - code.emit(MUL, targetReg, tmpLeft, tmpRight, "*"); + code.emit(MUL, targetReg, tmpLeft, targetReg, "*"); case Operators.DIV => - code.emit(DIV, targetReg, tmpLeft, tmpRight, "/"); + code.emit(DIV, targetReg, tmpLeft, targetReg, "/"); case Operators.MOD => - code.emit(MOD, targetReg, tmpLeft, tmpRight, "%"); + code.emit(MOD, targetReg, tmpLeft, targetReg, "%"); case _ => Console.println("unsupported BinOp: "+op); //TODO: does AND fit in here? what about other logic operations? } - } } case Block(stats, main) => @@ -230,11 +228,123 @@ //genTmp { tmpLeft => tree match { - case Binop(op, left, right) => - //op match { - // ... � compl�ter ... + case Binop(op, left, right) => { + genTmp { tmpLeft => + genTmp { tmpRight => + genLoad(left, tmpLeft); + genLoad(right, tmpRight); + op match { + case Operators.EQ => + code.emit(CMP, tmpLeft, tmpLeft, tmpRight, ""); + if ( when ) { + code.emit(BNE, tmpLeft, targetLabel); + } else { + code.emit(BEQ, tmpLeft, targetLabel); + } + + case Operators.NE => + code.emit(CMP, tmpLeft, tmpLeft, tmpRight, ""); + if ( when ) { + code.emit(BEQ, tmpLeft, targetLabel); + } else { + code.emit(BNE, tmpLeft, targetLabel); + } + + case Operators.ADD => + code.emit(ADD, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BNE, tmpLeft, targetLabel); + } else { + code.emit(BEQ, tmpLeft, targetLabel); + } + + case Operators.SUB => + code.emit(SUB, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BNE, tmpLeft, targetLabel); + } else { + code.emit(BEQ, tmpLeft, targetLabel); + } + + case Operators.MUL => + code.emit(MUL, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BNE, tmpLeft, targetLabel); + } else { + code.emit(BEQ, tmpLeft, targetLabel); + } + + case Operators.DIV => + code.emit(DIV, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BNE, tmpLeft, targetLabel); + } else { + code.emit(BEQ, tmpLeft, targetLabel); + } + + case Operators.MOD => + code.emit(MOD, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BNE, tmpLeft, targetLabel); + } else { + code.emit(BEQ, tmpLeft, targetLabel); + } + + case Operators.LT => + code.emit(SUB, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BLT, tmpLeft, targetLabel); + } else { + code.emit(BGE, tmpLeft, targetLabel); + } + + case Operators.LE => + code.emit(SUB, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BLE, tmpLeft, targetLabel); + } else { + code.emit(BGT, tmpLeft, targetLabel); + } + + case Operators.GT => + code.emit(SUB, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BGT, tmpLeft, targetLabel); + } else { + code.emit(BLE, tmpLeft, targetLabel); + } + + case Operators.GE => + code.emit(SUB, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BGE, tmpLeft, targetLabel); + } else { + code.emit(BLT, tmpLeft, targetLabel); + } + + case Operators.AND => + code.emit(AND, tmpLeft, tmpLeft, tmpRight); + if ( when ) { + code.emit(BNE, tmpLeft, targetLabel); + } else { + code.emit(BEQ, tmpLeft, targetLabel); + } + } + } + } + () + } - case Unop(op, expr) => () + case Unop(op, expr) => { + op match { + case Operators.NOT => + genCond(expr, targetLabel, !when); + case Operators.NEG => + genCond(expr, targetLabel, when); + + } + () + } // ... � compl�ter ... case _ => ()