diff --git a/sources/zweic/Generator.scala b/sources/zweic/Generator.scala
index 22f342b..e6ab424 100644
--- a/sources/zweic/Generator.scala
+++ b/sources/zweic/Generator.scala
@@ -166,15 +166,19 @@
 		genTmp { tmpReg =>
 		  op match {
 			case Operators.NOT => 
-			  genTmp { allOnes => 
-				code.emit(XOR, allOnes, ZERO, ZERO);
-				genLoad(expr, tmpReg);
-				code.emit(BIC, targetReg, allOnes, tmpReg);
-			  }			  
+				val store1 = code.getLabel();
+				val end = code.getLabel();
 
-		  case Operators.NEG => 
-			  genLoad(expr, tmpReg);
-			  code.emit(SUB, targetReg, ZERO, tmpReg, "-");
+				genCond(expr, store1, false);
+				emitLoadConstant(targetReg, 0);
+				code.emit(BEQ, ZERO, end);
+				code.anchorLabel(store1);
+				emitLoadConstant(targetReg, 1);
+				code.anchorLabel(end);
+
+			  case Operators.NEG => 
+				  genLoad(expr, tmpReg);
+				  code.emit(SUB, targetReg, ZERO, tmpReg, "-");
 		  }
 		}
 
@@ -194,8 +198,15 @@
 			  case Operators.MOD =>
 				code.emit(MOD, targetReg, tmpLeft, targetReg, "%");
 			  case _ =>
-				Console.println("unsupported BinOp: "+op);
-			  //TODO: does AND fit in here? what about other logic operations?
+				val store0 = code.getLabel();
+				val end = code.getLabel();
+
+				genCond(tree, store0, false);
+				emitLoadConstant(targetReg, 1);
+				code.emit(BEQ, ZERO, end);
+				code.anchorLabel(store0);
+				emitLoadConstant(targetReg, 0);
+				code.anchorLabel(end);
 			}
 		}
 
@@ -252,16 +263,11 @@
   } // genLoad
 
 
-
   /**
    * Generates code for conditions, that is constructs
    * which jump somewhere on the result of a test.
    */
   private def genCond(tree: Expr, targetLabel: code.Label, when: Boolean): Unit = {
-    // ... � compl�ter ...
-	
-	//genTmp { tmpLeft =>
-
     tree match {	  
 	case Binop(op, left, right) => {
 			genTmp { tmpLeft =>
@@ -364,6 +370,13 @@
 					} else {
 						code.emit(BEQ, tmpLeft, targetLabel);
 					}
+				case _ =>
+					genLoad(tree, tmpLeft);
+					if ( when ) {
+						code.emit(BNE, tmpLeft, targetLabel);
+					} else {
+						code.emit(BEQ, tmpLeft, targetLabel);
+					}
 			}
 			}
 			}
@@ -376,30 +389,14 @@
 					genCond(expr, targetLabel, !when);
 				case Operators.NEG =>
 					genCond(expr, targetLabel, when);
-					
 			}
 			()
 		}
-          // ... � compl�ter ...
 
-        case _ => ()
-          //TODO: caseDefault(tree)
-/*
-			  case Operators.EQ =>
-				code.emit(CMP, targetReg, tmpLeft, tmpRight, "*");
-
-			  case Operators.LT =>
-				//TODO
-			  case Operators.LE =>
-				//TODO				
-			  case Operators.GT =>
-				//TODO
-			  case Operators.GE =>
-				//TODO
-
-			  case Operators.AND =>
-				code.emit(AND, targetReg, tmpLeft, tmpRight, "*");
-*/		
+        case _ => 
+		assert(false, "mischt");
+		// TODO mischt ersetzte
+		()
     }
   } // genCond