diff --git a/sources/zweic/Generator.scala b/sources/zweic/Generator.scala
index e6ab424..142d549 100644
--- a/sources/zweic/Generator.scala
+++ b/sources/zweic/Generator.scala
@@ -163,24 +163,22 @@
 		code.emit(SYSCALL, targetReg, ZERO, SYS_IO_RD_CHR, "readChar")
 		
       case Unop(op, expr) =>
-		genTmp { tmpReg =>
-		  op match {
-			case Operators.NOT => 
-				val store1 = code.getLabel();
-				val end = code.getLabel();
+		op match {
+		  case Operators.NOT => 
+			val store1 = code.getLabel();
+			val end = code.getLabel();
+		  
+			genCond(expr, store1, false);
+			emitLoadConstant(targetReg, 0);
+			code.emit(BEQ, ZERO, end);
+			code.anchorLabel(store1);
+			emitLoadConstant(targetReg, 1);
+			code.anchorLabel(end);
 
-				genCond(expr, store1, false);
-				emitLoadConstant(targetReg, 0);
-				code.emit(BEQ, ZERO, end);
-				code.anchorLabel(store1);
-				emitLoadConstant(targetReg, 1);
-				code.anchorLabel(end);
-
-			  case Operators.NEG => 
-				  genLoad(expr, tmpReg);
-				  code.emit(SUB, targetReg, ZERO, tmpReg, "-");
+		  case Operators.NEG => 
+			genLoad(expr, targetReg);
+			code.emit(SUB, targetReg, ZERO, targetReg, "-");
 		  }
-		}
 
       case Binop(op, left, right) =>
 		genTmp { tmpLeft =>