diff --git a/sources/zweic/Generator.scala b/sources/zweic/Generator.scala
index c061372..2640bed 100644
--- a/sources/zweic/Generator.scala
+++ b/sources/zweic/Generator.scala
@@ -20,12 +20,15 @@
   }
 
   def emitLoadConstant(r: Int, value: Int) = {
-	if (value > (Math.pow(2,16) - 1)) {
-	  code.emit(ADDI, r, ZERO, value >> 16, value.toString());
-	  //TODO: SHIFT
-	  code.emit(ADDI, r, r, value << 16 >> 16);
+	val highBits = value >> 16;
+	val lowBits = value & 0xFFFF;
+
+	if (highBits != 0) {
+	  code.emit(ORIU, r, ZERO, highBits, value.toString()+"<<");
+	  code.emit(LSHI, r, r, 16, "<< 16");
+	  code.emit(ORIU, r, ZERO, lowBits, value.toString());
 	} else {
-	  code.emit(ADDI, r, ZERO, value, value.toString());
+	  code.emit(ORIU, r, ZERO, lowBits, value.toString());
 	}
   }
 
@@ -179,7 +182,11 @@
 		}
 
       case Block(stats, main) =>
-        // ... � compl�ter ...
+		//TODO: what about VarScope?
+		code.freeRegister(targetReg);
+		stats.foreach(gen);
+		code.getRegister(targetReg);
+		genLoad(main, targetReg);
 
       case Ident(name) =>
         // ... � compl�ter ...
@@ -194,17 +201,17 @@
         // ... � compl�ter ...
 
       case If(cond, thenp, elsep) =>
-		//TODO: this is absolutely wrong
-		val thenpos = code.getLabel();
-		val elsepos = code.getLabel();
-		genCond(cond, thenpos, true);
-		
-		genTmp { leftret =>
-		  genTmp { rightret =>			
-			genLoad(thenp, leftret);
-			genLoad(elsep, rightret);			
-		  }
-		}		
+		val elseLabel = code.getLabel();
+		val afterLabel = code.getLabel();
+
+		genCond(cond, elseLabel, false);
+		genLoad(thenp, targetReg);
+		code.emit(BEQ, ZERO, afterLabel);
+
+		code.anchorLabel(elseLabel);
+		genLoad(elsep, targetReg);
+		code.anchorLabel(afterLabel);
+
       case _ =>
 		Console.println("LoadGen________________");
         // ... � compl�ter ...