diff --git a/sources/zweic/Generator.scala b/sources/zweic/Generator.scala
index 94e8fff..0cc6089 100644
--- a/sources/zweic/Generator.scala
+++ b/sources/zweic/Generator.scala
@@ -102,7 +102,8 @@
 		  for ( val m <- cname.sym.asInstanceOf[ClassSymbol].allMethods ) {
 			//TODO: why use LNK here? don't we use a normal register???
 			emitLoadConstant(LNK, m.address);
-			code.emit(STW, LNK, classHeader, m.offset, 
+			//TODO: this +4 could be somewhere else....
+			code.emit(STW, LNK, classHeader, m.offset-4, 
 					  cname.name + "::" + m.name);
 		  }
 		}
@@ -152,7 +153,10 @@
 		val endwhile = code.getLabel();
 		val fs = code.getFrameSize();
 		code.anchorLabel(startwhile);
+
+		//TODO free targetregister
 		genCond(cond, endwhile, false);
+
 		stats.foreach(gen);
 		code.emit(SUBI, SP, SP, fs-code.getFrameSize());
 		code.decFrameSize(code.getFrameSize());
@@ -228,8 +232,11 @@
 		  case Operators.NOT => 
 			val storeTrue = code.getLabel();
 			val stored = code.getLabel();
-		  
+
+			code.freeRegister(targetReg);
 			genCond(expr, storeTrue, false);
+			code.getRegister(targetReg);
+
 			emitLoadConstant(targetReg, 0);
 			code.emit(BEQ, ZERO, stored);
 			code.anchorLabel(storeTrue);
@@ -260,7 +267,10 @@
 				val store0 = code.getLabel();
 				val end = code.getLabel();
 
+				code.freeRegister(targetReg);
 				genCond(tree, store0, false);
+				code.getRegister(targetReg);
+
 				emitLoadConstant(targetReg, 1);
 				code.emit(BEQ, ZERO, end);
 				code.anchorLabel(store0);
@@ -398,7 +408,10 @@
 		val elseLabel = code.getLabel();
 		val afterLabel = code.getLabel();
 
+		code.freeRegister(targetReg);
 		genCond(cond, elseLabel, false);
+		code.getRegister(targetReg);
+
 		genLoad(thenp, targetReg);
 		code.emit(BEQ, ZERO, afterLabel);
 
@@ -424,7 +437,7 @@
 				genLoad(left, tmpLeft);
 			genTmp { tmpRight =>
 				genLoad(right, tmpRight);
-
+			
 			op match {
 				// TODO do all this with CMP !!!
 				case Operators.EQ =>